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OKI Semiconductor ML2240
4-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
FEDL2240DIGEST-02
Issue Date: July 12, 2004
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
The ML2240 is a 4-channel mixing speech synthesis device which connects an external ROM expanded up to 128-Mbit (maximum). This ML2240 allows to select the playback method from the 8-bit PCM, non-linear 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms. And the sound volume is adjustable as well. The ML2240 incorporates a 14-bit D/A converter, and low-pass filter. It is easy to configure a speech synthesizer by externally connecting a power amplifier and a CPU to the ML2240.
FEATURES
* Non-linear 8-bit PCM, 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms * Serial input/parallel input selectable * Phrase control table function i.e., user definable phrase control table function * 4 channels mixing function * Master clock frequency: 4.096 MHz * Sampling frequency: 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, 21.3 kHz, 25.6 kHz, 32.0 kHz, 42.7 kHz, 48 kHz * Maximum number of phrases: 256 phrases * Sound volume adjustment function built in (4 sounds independently adjustable in 29 steps) * External voice data can be input * 14-bit D/A converter built in * Built-in low-pass filter: Digital filter * Package: 80-pin plastic TQFP (TQFP80-P-1212-0.50-K) (ML2240TB)
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BYTE A22
*****
A0 RD14
***** *****
RD15/A-1
RD0
OKI Semiconductor
*****
BLOCK DIAGRAM
23bit Multiplexer 16bit Latch
23bit Address Controller
2bit ADPCM2 4bit ADPCM2 Synthesizer 8bit PCM 16bit PCM Synthesizer&2ch Mix
CPU interface
Command Contoroller Volume Digital Filter
OPTANA RD SERIAL D7/DI D6/SCK D5/DO D4/STASEL D3/STA3 D2/STA2 D1/STA1 D0/STA0 WR CS ROE RCS 14bit DAC Timing Controller DASEL DASD DASCK
XT XT
OSC
AVDD AGND
FEDL2240DIGEST-02
ML2240 Family
DVDD DGND
RESET
TEST
AOUTL AOUTR DAOL DAOR
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ML2240 Family
PIN CONFIGURATION (TOP VIEW)
80-pin plastic TQFP
RD13 RD6 RD14 DGND RD7 RD15/A-1 BYTE RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RD5 RD12 RD4 RD11 RD3 RD10 RD2 RD9 DVDD DVDD DVDD DGND RD1 RD8 RD0 TEST DASEL DASD DASCK NC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC SERIAL ROE DGND RCS AVDD AOUTR DAOR NC AOUTL DAOL AGND D7/DI D6/SCK D5/DO D4/STASEL D3/STA3 D2/STA2 D1/STA1 D0/STA0
DVDD RA13 RA14 RA15 XT NC XT RA16 RA17 RA18 DGND RA19 RA20 RA21 RA22 RESET WR RD CS OPTANA NC: No Connection
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ML2240 Family
PIN DESCRIPTIONS
80-pin Plastic TQFP
Pin 1-3, 5, 66-68, 73-80 Symbol Type Description Data pins to connect an external memory. Data is input when the ROE pin is at "L" level. Input data from outside is not accepted when the ROE pin is at "H" level. The RD14-RD8 pins do not accept input data from outside when the BYTE pin is at "L" level. Data pin of the externally connected memory when BYTE pin is at "H" level. The data is input when the ROE pin output is at "L" level. When the ROE pin output is at "H" level, input data from outside is not accepted. This pin becomes an address A-1 output pin when the device is in byte mode. The address is output when the RCS pin is at "L" level. When the RCS pin is at "H" level, this pin is in a high impedance state. Word/byte switching pin of the externally connected memory. When BYTE pin = "L" level: Byte mode When BYTE pin = "H" level: Word mode Address pins of an externally connected memory. When RCS pin = "H": High impedance Wired to a crystal or ceramic oscillator. Contains a feedback resistor of around 1 M between this XT pin and XT pin (pin 27). When using an external clock, input the clock from this pin. Wired to a crystal or ceramic oscillator. When using an external clock, keep this pin open. When "L" level is input to this pin, the device is reset to the initial state. The oscillation stops, and AOUT output goes into "GND" level. CPU interface write signal. When CS pin is at "H" level, the WR signal cannot be input to the device. CPU interface read signal. For parallel input interface, a status signal for each channel is output from the D0-D7 pins when the RD pin is at "L" level. For the serial input interface, a status signal for each channel is output from the D5/D0 pin. This pin has a pull-up resistor built-in. CPU interface chip select pin. When CS pin is at "H" level, the WR, and RD signals cannot be input to the device. CPU interface data bus pins in the parallel input interface become data input pins when WR is at "L" level. They become channel status output pins in the serial input interface. These pins also become channel status output pins when RD is at "L" level.
RD14-RD0
I
6
RD15/A-1
I/O
7 8-20, 22-24, 28-30, 32-35 25
BYTE RA22-RA0
I O
XT
I
27 36 37
XT RESET WR
O I I
38
RD
I
39
CS D3/STA3 D2/STA2 D1/STA1 D0/STA0
I
41-44
I/O
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ML2240 Family
Pin No.
Pin Symbol
I/O
45
D4/STASEL
I/O
46
D5/DO
I/O
47
D6/SCK
I/O
48
D7/DI
I/O
50 51 53 54 56 58 59
DAOL AOUTL DAOR AOUTR RCS ROE SERIAL
O O O O I O I
Description CPU interface data bus pin in the parallel input interface. This pin becomes a data input pin when WR is at "L" level. It becomes a channel status output pin when RD is at "L" level. It outputs a BUSY signal for channel 1. For the serial input interface, it becomes a channel status changeover pin. When D4/STASEL is at "L" level, the D3/STA3-D0/STA0 pins output the NCR (Next Command Request) for each channel. When the D4/STASEL is at "H" level, the D3/STA3-D0/STA0 pins output BUSY signals for their corresponding channels. CPU interface data bus pin in the parallel input interface. This pin becomes a data input pin when WR is at "L" level. It becomes a channel status output pin when RD is at "L" level. This pin outputs 2 channels of BUSY signal. When CS and RD are at "L" level, this D5/DO pin serially outputs the status of each channel in synchronization with D6/SCK clock. CPU interface data bus pin in the parallel input interface. This pin becomes a data input pin when WR is at "L" level. It becomes a channel status output pin when RD is at "L" level. It outputs a BUSY signal for channel 3. This pin becomes a serial clock input pin for the serial input interface. When the SCK pin input is at "L" level on the falling edge of the CS pin signal, the DI pin input signal goes into the device on at the rising edge of the SCK clock, and the data is output from the DO pin. When the SCK pin input is at "H" level on the falling edge of the CS pin signal, the DI pin input signal goes into the device on the falling edge of the SCK clock, and the data is output from the DO pin. CPU interface data bus pin in the parallel input interface. When WR is at "L" level, it becomes a data input pin. When RD is at "L" level, it becomes a channel status output pin. It outputs a BUSY signal for channel 4. For the serial input interface, this pin becomes a serial data input pin. Works as serial data input pin in the serial input interface. Outputs the left 14-bit DAC analog signal. Outputs the left 14-bit DAC analog signal via voltage follower. Outputs the right 14-bit DAC analog signal. Outputs the right 14-bit DAC analog signal via voltage follower. "L" level: RA22-0, A-1, and ROE pins output the address data and the output enable signal. "H" level: RA22-0, A-1, and ROE pins are in high impedance. Output enable pin for an externally connected memory. RCS pin = "H" level: High impedance CPU interface switching pin. "H" level: Serial input interface, "L" level: Parallel input interface
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ML2240 Family
Pin No. 40 62 63 64 65
Pin Symbol OPTANA DASCK DASD DASEL TEST
I/O I O O O I
55
AVDD
--
21, 70-72 49 4, 31, 57, 69
DVDD AGND DGND
-- -- --
Description Device test pin. Fix this pin to "L" level. Device test pin. Leave this pin open. Device test pin. Leave this pin open. Device test pin. Leave this pin open. Device test pin. Input "L" level. This pin has a pull-down resistor built in. Analog power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and AGND pin. Digital power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and DGND pin. Analog ground pin. Digital ground pin.
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta = 25C -- Rating -0.3 to +7.0 -0.3 to VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (3 V)
(GND = 0 V) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition -- -- -- Min. 3.5 Range 2.7 to 3.6 -40 to +85 Typ. 4.096 Max. 4.5 Unit V C MHz
RECOMMENDED OPERATING CONDITIONS (5 V)
(GND = 0 V) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition -- -- -- Min. 3.5 Range 4.5 to 5.5 -40 to +85 Typ. 4.096 Max. 4.5 Unit V C MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics (3 V)
DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 (Note 1) "H" input current 3 (Note 4) "L" input current 1 "L" input current 2 (Note 2) "L" input current 3 (Note 1) Output leakage current (Note 3) Operating current consumption 1 Operating current consumption 2 Standby current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 ILO IDD1 IDD2 IDS Condition -- -- IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD VIL = GND VIL = GND VIL = GND 0 VOUT VDD fOSC = 4 MHz at no load OPTANA = "L" fOSC = 4 MHz at no load OPTANA = "H" Ta = -40 to +70C Ta = -40 to +85C Min. 0.86 x VDD -- VDD - 0.4 -- -- 0.3 8 -10 -120 -15 -10 -- -- -- -- Typ. -- -- -- -- -- 3.0 -- -- -- -3.0 -- 8 10 -- -- Max. -- 0.14 x VDD -- 0.4 10 15 130 -- -10 -0.3 +10 20 30 15 50 Unit V V V V A A A A A A A mA mA A A
Notes: 1. 2. 3. 4.
Applies to XT pin. Applies to RD pin. Applies to RA22 to RA0, D15/A-1, and ROE pins. Applies to TEST pin.
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ML2240 Family
DC Characteristics (5 V)
DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 (Note 1) "H" input current 3 (Note 4) "L" input current 1 "L" input current 2 (Note 2) "L" input current 3 (Note 1) Output leakage current (Note 3) Operating current consumption 1 Operating current consumption 2 Standby current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 ILO IDD1 IDD2 IDS Condition -- -- IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD VIL = GND VIL = GND VIL = GND 0 VOUT VDD fOSC = 4 MHz at no load OPTANA = "L" fOSC = 4 MHz at no load OPTANA = "H" Ta = -40 to +70C Ta = -40 to +85C Min. 0.8 x VDD -- VDD - 0.4 -- -- 0.8 30 -10 -230 -20 -10 -- -- -- -- Typ. -- -- -- -- -- 5.0 -- -- -- -5.0 -3.0 14 17 -- -- Max. -- 0.2 x VDD -- 0.4 10 20 350 -- -60 -0.8 +10 30 40 15 100 Unit V V V V A A A A A A A mA mA A A
Notes: 1. 2. 3. 4.
Applies to XT pin. Applies to RD pin. Applies to RA22 to RA0, D15/A-1, and ROE pins. Applies to TEST pin.
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Analog Section Characteristics (3 V)
DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter AOUT, AOUTR output load resistance AOUT, AOUTR output voltage range DAOL, DAOR output impedance Symbol RLAO VAOUT RDAO Condition -- No output load -- Min. 50 0.5 30 Typ. -- -- 43 Max. -- AVDD - 0.5 60 Unit k V k
Analog Section Characteristics (5 V)
DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter AOUT, AOUTR output load resistance AOUT, AOUTR output voltage range DAOL, DAOR output impedance Symbol RLAO VAOUT RDAO Condition -- No output load -- Min. 50 0.5 30 Typ. -- -- 43 Max. -- AVDD - 0.5 60 Unit k V k
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FUNCTIONAL DESCRIPTION
Micro-computer Interface The micro-computer interface in the ML2240 has 2 types of interface circuits built in: Parallel interface and serial interface. The interface setting can be changed with the SERIAL pin. SERIAL pin = "H" level: Serial interface SERIAL pin = "L" level: Parallel interface Table below shows the SERIAL pin status in the serial and parallel interfaces.
SERIAL = "L" Parallel interface D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) Data input and output pins/ status output pin D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) STA3 (O) STA2 (O) STA1 (O) STA0 (O) STASEL (I) DI (I) SCK (I) DO (O) SERIAL = "H" Serial interface Serial data input pin Serial clock input pin Channel status serial output pin Channel status switching pin NCRn output at "L" level BUSYn output at "H" level Channel 4 status output pin Channel 3 status output pin Channel 2 status output pin Channel 1 status output pin
1. Parallel Interface When selecting the parallel interface, the I/O pins CS, WR, D7 to D0, and RD are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data input. The micro-computer interface becomes effective when the CS pin is set to "L" level. When a command or data is input, the input data to D7 through D0 pins is captured inside the device on the rising edge of the WR pin. To read the channels status, pins CS and RD are made "L" level. By doing so, the status signals of each channel are output to D7 through D0 pins.
Command and Data Input Timing
CS (I) WR (I)
D7 to D0 (I/O)
Data Stable
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Status Read Timing
CS (I) RD (I)
D7 to D0 (I/O)
Data Stable
Table below shows the contents of each data output when reading the status of the channels.
Pin D7 D6 D5 D4 D3 D2 D1 D0 Output status signal Channel 4 BUSY output (BUSY4) Channel 3 BUSY output (BUSY3) Channel 2 BUSY output (BUSY2) Channel 1 BUSY output (BUSY1) Channel 4 NCR output (NCR4) Channel 3 NCR output (NCR3) Channel 2 NCR output (NCR2) Channel 1 NCR output (NCR1)
The BUSY signal outputs "L" level when either a command is being processed or the playback of a pertinent channel is going on. In other states, the BUSY signal outputs "H" level. The NCR signal outputs "L" level when either a command is being processed or a pertinent channel is in standby for playback. In other states, the NCR signal outputs "H" level.
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ML2240 Family
2. Serial Interface When selecting the serial interface, the I/O pins CS, WR, DI. SCK, RD, and DO are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data. The micro-computer interface becomes effective when CS pin is set to "L" level. To input the commands and data, "L" level is input to CS and WR pins followed by, from MSB, to DI pin in synchronization with the input clock signal at SCK pin. Data at DI pin is captured inside the device on the rising or falling edge of the clock at SCK pin. And the command is executed on the rising edge of the WR pin. The selection of rising/falling edge of SCK clock is determined by the input level of the SCK pin on the falling edge of the CS pin. If the SCK pin on the falling edge of the CS pin is at "L" level, the DI pin data is captured inside the device on the rising edge of SCK clock. Conversely, if the SCK pin on the falling edge of the CS pin is at "H" level, then the DI pin data is captured on the falling edge of SCK clock.
Command and Data Input Timings * SCK Rising Edge Operation
CS (I) WR (I)
DI (I)
D7 D6 D5 D4 D3 D2 D1 D0
SCK (I)
* SCK falling Edge Operation
CS (I) WR (I)
DI (I)
D7 D6 D5 D4 D3 D2 D1 D0
SCK (I)
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To read the channel status, input "L" level to CS and RD pins. D0 pin will output the channel status in synchronization with SCK clock. The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined by the level at SCK pin at the falling edge of CS pin. The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7. Status Read Timing * SCK Rising Edge Operation
CS (I) RD (I)
SCK (I) Hi-Z Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
* SCK Falling Edge Operation
CS (I) RD (I)
SCK (I) Hi-Z Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
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Commands List Each command is 1-byte (8 bits) input. PLAY, MUON, and FLASH I/F only are 2 bytes input.
Command PUP1 PUP2 PDWN1 PDWN2 D7 0 0 0 0 0 PLAY F7 F6 F5 F4 F3 F2 F1 F0 D6 0 0 0 0 1 D5 0 0 1 1 0 D4 0 1 0 1 0 D3 C3 D2 C2 D1 C1 D0 C0 Description Instantly shifts the power down device to the command standby state. Suppresses pop noise and shifts the power down device to the command standby state. Instantly shifts the device from the command standby state to the power down state. Suppresses pop noise and shifts the device from the command standby state to power down state. Inputs the phrase after the playback channel is specified, and then starts the playback. Playback start command with phrase specification. Inputs the phrase after the playback channel is specified, and then starts the playback. Playback start command without phrase specification. Inputs the phrase with the FADR command and starts the playback on multiple channels at the same time. Phrase specification command. With this command, specifies the playback phrase for each channel. Playback stop command. Specifies the channel for inserting silence, inputs the silence duration, and then inserts silence. Repeats the playback mode setting command. Effective only for the channel being used for playback. Repeat playback mode releasing command. Inputting the STOP command releases repeat playback mode automatically. Specifies the channel for which the sound volume is to be set, and then sets the volume for that channel. Sets the volume for the Left/Right of each channel.
START
0
1
0
1
C3
C2
C1
C0
0 FADR F7 STOP MUON M7 SLOOP 1 0 1
1 F6 1 0 M6 0
1 F5 1 0 M5 0
0 F4 1 0 M4 1
C3 F3 C3 C3 M3 C3
C2 F2 C2 C2 M2 C2
C1 F1 C1 C1 M1 C1
C0 F0 C0 C0 M0 C0
CLOOP
1 1
0 0 1
1 1 0
0 1 V4 0 L4 R4
C3 C3 V3 C3 L3 R3
C2 C2 V2 C2 L2 R2
C1 C1 V1 C1 L1 R1
C0 C0 V0 C0 L0 R0
VOL
1
PAN
C3, C2, C1, C0 F7 to F0 M7 to M0 V4 to V0 L4 to L0 R4 to R0
: Channel specification (C3 = "1": Channel 4; C2 = "1": Channel 3; C1 = "1": Channel 2, C0 = "1": Channel 1) : Phrase address : Silence time length : Sound volume : Left sound volume : Right sound volume
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Power Down Function In power down state, the power down function in the device stops the internal operation and oscillation, sets AOUT to GND, and minimizes the static Idd. Figure below shows the equivalent circuit of XT and XT pins.
To master clock inside the device 1 M approx.
RESET External input
XT "L"
XT "L"
Channel Status Channel status is of 2 types: NCRn and BUSYn.
Channel CH1 CH2 CH3 CH4 Channel status NCR1 NCR2 NCR3 NCR4 BUSY1 BUSY2 BUSY3 BUSY4
NCRn = "H" indicates that it is possible to input the PLAY, START, and MUON commands for the phrase to be played back next for channel n. BUSYn = "H" indicates a state in which channel n has not performed voice processing. BUSYn = "L" indicates a state in which channel n is performing voice processing. Meanwhile, after a command is input, the NCR and BUSY signals of all channels are at "L" level during the processing of the command. For Status output methods, see the Micro-computer Interface section.
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Voice Synthesis Algorithm The ML2240 contains 5 algorithm types to match the characteristic of playback voice: 2-bit ADPCM 2 algorithm, 4-bit ADPCM 2 algorithm, 8-bit PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit PCM algorithm. Key feature of each algorithm is described in the table below.
Voice synthesis algorithm Oki 2-bit ADPCM2 Applied waveform Normal voice waveform Feature Oki's specific speech synthesis algorithm of low bit rate with improved 2-bit ADPCM. Oki's specific speech synthesis algorithm of improved waveform follow-up with improved 4-bit ADPCM. Algorithm which plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm
Oki 4-bit ADPCM2
Normal voice waveform High-frequency components inclusive sound effect etc. High-frequency components inclusive sound effect etc. High-frequency components inclusive sound effect etc.
Oki 8-bit Nonlinear PCM 8-bit PCM 16-bit PCM
Memory Allocation and Creating Voice Data The ROM is partitioned into 3 data areas: voice (i.e., phrase) control area, voice area, and phrase control table area. The voice control area manages the ROM's voice data. It controls the start/end addresses of voice data, usage/not usage of the phrase control table function and so on. The voice control area stores voice control data for 256 phrases. The voice area stores the actual waveform data. The phrase control table area stores data for effective use of voice data. As for the details, please refer to the Phrase control table Function. There is no phrase control table area if the phrase control table is not used. The ROM data is created using a development tool.
ROM Addresses (ML2240 byte mode) 0x000000 0x0007FF 0x000800 Voice control area (16 Kbit Fixed)
Voice area
max: 0xFFFFFF Phrase control table area Depends on creation of ROM data.
max: 0xFFFFFF
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Playback Time and Memory Capacity The playback time depends upon the memory capacity, sampling frequency, and playback method. The equation showing the relationship is given below. 1.024 x (Memory capacity - 16) (Kbit) Playback time [sec] = Sampling frequency (kHz) x Bit length (Bit length is ADPCM, ADPCM 2 = 4 bits; PCM = 8 bits.) Example: Let the sampling frequency be 16 kHz and 4-bit ADPCM algorithm. If one 8 Mbits ROM is used, then the playback time is obtained as follows: 1.024 x (8192 - 16) (Kbit) 16 (kHz) x 4 (bit) 131 (sec)
Playback time =
The above equation gives the playback time when the phrase control table function is not used.
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Mixing Function The ML2240 can perform simultaneous mixing of 4 channels. It is possible to specify PLAY and STOP for each channel separately. * Precautions for Waveform Clamp at the Time of Channels Mixing When mixing of channels is done, the clamp occurrence possibility increases from the mixing calculation point of view. If it is known beforehand that the clamp will occur, then adjust the sound volume by VOL command. * Mixing of Different Sampling Frequency It is not possible to perform analog mixing by a different sampling frequency. When performing analog mixing, the sampling frequency group of the first playback channel is selected. Therefore, please note that if analog mixing is performed by a sampling frequency group other than the selected sampling frequency group, then the playback will not be of constant speed: some times faster and at other times slower. The available sampling groups for analog mixing by a different sampling frequency are listed below. 4.0 kHz, 8.0 kHz, 16.0 kHz, 32.0 kHz *** (Group 1) 5.3 kHz, 10.6 kHz, 21.3 kHz, 42.7 kHz *** (Group 2) 6.4 kHz, 12.8 kHz, 25.6 kHz *** (Group 3) Figures below show a case when a sampling frequency group played back a different sampling frequency group.
fs = 16.0 kHz Channel 1 fs = 25.6 kHz (Invalid. Played back as fs = 32.0 kHz.) Channel 2
Figure 1 In Case a Different Sampling Frequency Played Back during Playback of the Other Channel Playback
fs = 16.0 kHz Channel 1
Normal playback if not played back by other channel.
fs = 25.6 kHz (Valid) Channel 2 End of channel 1
Figure 2 In Case a Different Sampling Frequency Played Back after the End of the Other Channel
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Phrase Control Table Function The phrase control table function makes it possible to play back multiple phrases in succession. The following functions are set using the phrase control table function: * Continuous playback: There is no limit to the number of times a continuous playback can be specified. It depends on the memory capacity only. * Silence insertion function: 4 to 1024 ms Using the phrase control table function enables to effectively use the memory capacity of voice ROM. Below is an example of the ROM configuration in the case of using the phrase control table function.
Example 1: Phrases Using the Phrase Control Table Function
Phrase 1 Phrase 2 Phrase 3 Phrase 4 Phrase 5
A A E E A B C
B C D D B
D D
D
Silence
E
C
D
Example 2: Example of ROM Data in case Example 1 Converted to ROM
Address control area A B D C E F Editing area
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APPLICATION CIRCUIT EXAMPLE
MCU RESET CS WR RD 8 D7-0 18 SERIAL BYTE RCS ROE OPTANA TEST 30pF XT 4.096MHz XT 30pF Speaker driver AOUTR Speaker AOUTL Speaker driver Speaker RA17-0 RD15/A-1 RD7-0 8 A18-1 A0 D7-0 OE A18-1 A0 D7-0 OE A18-1 A0 D7-0 OE A18-1 A0 D7-0 OE RA19 RA18 74HC139 Y3 2B Y2 2A Y1 Y0 1G 2G MSM27C401CZ CE CE CE CE
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP80-P-1212-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.40 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
REVISION HISTORY
Page Document No. Date Previous Edition 15 Current Edition 15 Final edition 1 Corrected first byte of Play command. Description
FEDL2240DIGEST-01 FEDL2240DIGEST-02
Oct. 17, 2003 Jul. 12, 2004
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FEDL2240DIGEST-02
OKI Semiconductor
ML2240 Family
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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